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Instruction set architecture
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#	Item
341	HP OpenVMS Calling Standard Order Number: AA–QSBBE–TE January 2005 This standard defines the requirements, mechanisms, and conventions that support procedure-to-procedure calls for HP OpenVMS VAX, HP OpenVMS Alpha, a Add to Reading List Source URL: www.openvms.compaq.com Language: English - Date: 2008-03-10 11:53:07 Instruction set architectures Cluster computing Hewlett-Packard OpenVMS Parallel computing Call stack Subroutine Stack DEC Alpha Computing Computer architecture Computer programming
342	Vector IRAM: ISA and Micro-architecture Christoforos E. Kozyrakis Computer Science Division University of California, Berkeley Add to Reading List Source URL: iram.cs.berkeley.edu Language: English - Date: 1998-08-24 18:37:00 Computer engineering Vector processor Instruction set Vector Computer Microarchitecture The Berkeley IRAM Project Central processing unit Computer architecture Computing
343	HP OpenVMS MACRO Compiler Porting and User’s Guide Order Number: AA–PV64E–TE January 2005 This manual describes how to port Macro-32 source code written for the VAX MACRO compiler to the MACRO compiler for OpenVMS Add to Reading List Source URL: www.openvms.compaq.com Language: English - Date: 2008-03-10 11:53:00 OpenVMS VAX Macro VAX DEC Alpha Itanium 64-bit EVE Assembly language HP BASIC for OpenVMS Computing Computer architecture Instruction set architectures
344	HP OpenVMS Guide to Upgrading Privileged-Code Applications Order Number: AA–QSBGE–TE January 2005 Add to Reading List Source URL: www.openvms.compaq.com Language: English - Date: 2008-03-10 11:53:25 Instruction set architectures OpenVMS Cluster computing Hewlett-Packard Asynchronous System Trap DEC Alpha 64-bit Operating system X Window System Computing Computer architecture Digital Equipment Corporation
345	Imperial College London Department of Computing Add to Reading List Source URL: www.doc.ic.ac.uk Language: English - Date: 2009-10-22 13:42:54 Computer memory Instruction set architectures Central processing unit Assembly languages Minicomputers Memory address Addressing mode Motorola 68000 CPU cache Computer architecture Computer hardware Computing
346	Are Your Passwords Safe: Energy-Efficient Bcrypt Cracking with Low-Cost Parallel Hardware Katja Malvoni (kmalvoni at openwall.com) Add to Reading List Source URL: www.usenix.org Language: English - Date: 2014-11-11 15:42:08 Cryptographic software System software Instruction set architectures Password Crypt John the Ripper ARM architecture Central processing unit Field-programmable gate array Software Computer architecture Bcrypt
347	Microsoft Word - Arch_WhitePaperB2 _2__6_12_09.doc Add to Reading List Source URL: www.chipwrights.com Language: English - Date: 2009-10-01 18:55:24 Electronic engineering Datapath Register file Instruction set ARM architecture Accumulator Processor register Memory address No instruction set computing Computer architecture Central processing unit Computer hardware
348	7th April 1994 Support Group Application Note Number: 256 Issue: 1.00 Author: JR/JB Add to Reading List Source URL: chrisacorns.computinghistory.org.uk Language: English - Date: 2013-08-13 09:33:18 ALGOL 68 Instruction set 26-bit ARM architecture Acorn Computers FLAGS register Computer architecture Computing Instruction set architectures
349	ARM 7TDMI Data Sheet Issued: August 1995 Copyright Advanced RISC Machines Ltd (ARMAll rights reserved Add to Reading List Source URL: www.ndsretro.com Language: English - Date: 2006-12-01 15:44:11 Central processing unit Instruction set architectures ARM architecture Embedded systems ARM7 Instruction set Joint Test Action Group Reduced instruction set computing Microprocessor Computer architecture Computer hardware Electronic engineering
350	Developments in KVM on Power Paul Mackerras, IBM LTC OzLabs Add to Reading List Source URL: www.linux-kvm.org Language: English - Date: 2013-11-02 19:08:59 Virtual machines Instruction set architectures Computer memory Data transmission Endianness QEMU PowerPC Hypervisor Paravirtualization System software Software Power Architecture

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